The present invention relates to a test circuit for testing Input/Output macrocell of erasable and programmable logic device.
EPROM(Erasable Programmable Read Only Memory) transistors necessary to manufacture the Erasable and Programmable Logic Device(hereinafter referred to as EPLD) are erased by ultraviolet rays, and are programed electrically. In case that EPROM memory array is programmed in order to test the programmed state, it was impossible to test I/O(Input/Output) macrocell because the I/O macrocell is connected to the output of the EPROM memory array and I/O macrocell is fixed according to the programmed EPROM transistors.
The prior art for the I/O macrocell test circuit is shown in FIG. 1. In FIG. 1, a test circuit 2 is comprised between the Programmable "AND" memory array 1 and the I/O macrocell 3, and the test circuit 2 is composed of some extra test lines and the EPROM transistors connected to each extra test line.
In order to test the Input/Output macrocell, a part of the EPROM transistors are programmed and through the extra test line the data are transmitted to the Input/Output macrocell.
The problem in said test is to program a part of the EPROM transistors.